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fe atures fas t ac ces s tim e : 55ns low power consumption: operating current:30 ma (typ.) standby current : 4 a (typ.) ll-version singl e 2.7 v~ 5.5v pow er supply all inputs and outputs ttl compatible fully static operation tri-state output da ta by te control : lb# (dq0 ~ dq7) ub# ( dq 8 ~ dq15) data retention voltage : 1.5 v(min.) lead free and green pa ck age available package : 44-pin 400 mil tsop-ii 48-ball 6mm x 8mm tfbga general description the is a 4,194,304-bit low power cmos static random access memory organized as 262,144 words by 16 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. the op erates f roma si ngl e po wer supply of 2.7v ~ 5.5v and all inputs and outputs are fully ttl co mpatible product family power di ss ipation product family operating temperature vc c range speed standby(i sb1, typ.) o peratin g(icc ,typ.) (i) -40 ~ 85 2.7 ~ 5.5v 55ns 4a(ll) 30ma functional block diagram t o o r t i o v ou oo u r l ww l aa c c r yy 2 c/2 c c m7 2 c/2 t o r t r pin de scription symbol description a0 - a17 address inputs dq0 ? dq15 data inputs/outputs ce# chip enable input we# write enable input oe# output enable input lb# lowe r byte control ub# upper byte control v cc power supply v ss ground 512kx 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 1 of 12 AS6C4016 256k x 16 bit super low power cmos sram
pin configuration a1 a2 a3 a4 dq15 dq0 dq1 dq2 vcc vss a12 a17 dq14 dq12 dq13 dq11 vss vcc dq10 dq9 dq3 dq4 tsop ii a16 a0 dq6 dq7 a5 a6 a7 a8 a9 dq5 dq8 a15 a14 a13 a10 nc a11 ce# we# lb# ub# oe# t c c c l aa c l ww l ww c l aa c c c r c c c c c c c c absolute maximun ratings* parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 6.5 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) t solder 260 *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to the absolute maximum rating conditions for extended period may affect device reliability. 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 2 of 12 AS6C4016 256k x 16 bit super low power cmos sram
t ru th table i/o operation mode ce# oe# we# lb# ub# dq0-dq7 dq8-dq15 su pp ly current standby h x x x x x x h x h high?z high?z high?z high?z i sb1 output disable l l h h h h l x x l high?z high?z high?z high?z i cc ,i cc1 re ad l l l l l l h h h l h l h l l d out high?z d out high?z d out d out i cc ,i cc1 wr ite l l l x x x l l l l h l h l l d in high?z d in high?z d in d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electri cal charac teristics para me ter symbol test condition min. typ. *3 max. unit supply voltage v cc 2.7 3.0 5.5 v input high voltage v ih *1 2.4 - v cc +0.3 v input low voltage v il *1 - 0.2 - 0.6 v input leakage current i li v cc v in v ss - 1 - 1 a output leakage current i lo v cc v out v ss output disabled - 1 - 1 a output high voltage v oh i oh = -1ma 2.4 - - v output low voltage v ol i ol = 2ma - - 0.4 v - 55 - 30 60 ma i cc cycle time = min. ce# = v il , i i/o = 0ma other pins at v il or v ih average operating power supply current i cc1 cy cle time = 1 s ce# 0.2v, i i/o = 0ma othe r pins at 0.2v or v cc -0.2v - 4 10 ma standby power supply current i sb1 ce# v cc -0.2v others at 0.2v or v cc -0.2v lli - 4 50 *4 a notes: 1. v ih (max) = v cc + 3.0v for pulse width le ss than 10ns. v il (min) = v ss - 3.0v for pulse width le ss than 10ns. 2. ov er/undershoot specifications are characterized, not 100% tested. 3. typical values are included for reference only and are not guara nteed or tested. typical values are measured at v cc = v cc (typ.) and t a = 25 4. 25 a for special request cap ac ita nce (t a = 25 , f = 1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device chara ct erization, but not product ion tested. 512kx 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 3 of 12 AS6C4016 256k x 16 bit super low power cmos sram
ac test conditions input pulse levels 0.2v to v cc - 0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh /i ol = -1ma/2ma ac electrical characteristics (1) read cycle AS6C4016 -55 parameter sym. min. max. unit read cycle time t rc 55 - ns address access time t aa - 55 ns chip enable access time t ace - 55 ns output enable access time t oe - 30 ns chip enable to output in low-z t clz * 10 - ns output enable to output in low-z t olz * 5 - ns chip disable to output in high-z t chz * - 20 ns output disable to output in high-z t ohz * - 20 ns output hold from address change t oh 10 - ns lb#, ub# access time t ba - 55 ns lb#, ub# to high-z output t bhz * - 25 ns lb#, ub# to low-z output t blz * 10 - ns (2) write cycle AS6C4016 -55 parameter sym. min. max. unit write cycle time t wc 55 - ns address valid to end of write t aw 50 - ns chip enable to end of write t cw 50 - ns address set-up time t as 0 - ns write pulse width t wp 45 - ns write recovery time t wr 0 - ns data to write time overlap t dw 25 - ns data hold from end of write time t dh 0 - ns output active from end of write t ow * 5 - ns write to output in high-z t whz * - 20 ns lb#, ub# valid to end of write t bw 45 - ns *these parameters are guaranteed by device characterization, but not production tested. 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 4 of 12 AS6C4016 256k x 16 bit super low power cmos sram
timing waveforms read cycle 1 (address controlled) (1,2) read cycle 2 (ce# and oe# controlled) (1,3,4,5) dout data valid high-z high-z t clz t olz t chz t ohz t oh oe# t oe lb#,ub# t bhz t ace ce# t aa address t rc t ba t blz notes : 1.we#is high for read cycle. 2.device is continuously selected oe# = low, ce# = low, lb# or ub# = low . 3.address must be valid prior to or coincident with ce# = low, lb# or ub# = low transition; otherwise t aa is the limiting parameter. 4.t clz , t blz, t olz , t chz, t bhz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5.at any given temperature and voltage condition, t chz is less than t clz , t bhz is less than t blz , t ohz is less than t olz. 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 5 of 12 AS6C4016 256k x 16 bit super low power cmos sram
write cycle 1 (we# controlled) (1,2,3,5,6) write cycle 2 (ce# controlled) (1,2,5,6) 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 6 of 12 AS6C4016 256k x 16 bit super low power cmos sram
write cycle 3 (lb# ,ub# controlled) (1,2,5,6) notes : 1.we#,ce#, lb#, ub# must be high during all address transitions. 2.a write occurs during the overlap of a low ce#, low we#, lb# or ub# = low. 3.during a we# controlled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be placed on the bus. 4.during this period, i/o pins are in the output state, and input signals must not be applied. 5.if the ce#, lb#, ub# low transition occurs simultaneously with or after we# low transition, the outputs remain in a high impedance state. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 7 of 12 AS6C4016 256k x 16 bit super low power cmos sram
data retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v cc - 0.2v 1.5 - 5.5 v data retention current i dr v cc = 1.5v, ce# v cc -0.2v others at 0.2v or v cc -0 .2v ll i - 2 30 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns re co very time t r t rc * - - ns t rc * = re ad cycle time data retention waveform low vcc data retention waveform (1) (ce# controlled) vcc ce# v dr 1.5 v ce# v cc-0.2v vcc(min.) v ih t r t cdr v ih vcc(min.) low vcc data retention waveform (2) (l b#, ub# controll ed) vcc lb#,ub# v dr 1.5 v lb#,ub # v cc-0 .2v vcc (min.) v ih t r t cdr v ih vcc(min.) 512kx 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 8 of 12 AS6C4016 256k x 16 bit super low power cmos sram
package outline dimension 44-pin 400mil tsop- package outline dimension dimensions in millmeters dimensions in mils symbols min. nom. max. min. nom. max. a - - 1.20 - - 47.2 a1 0.05 0.10 0.15 2.0 3.9 5.9 a2 0.95 1.00 1.05 37.4 39.4 41.3 b 0.30 - 0.45 11.8 - 17.7 c 0.12 - 0.21 4.7 - 8.3 d 18.212 18.415 18.618 717 725 733 e 11.506 11.760 12.014 453 463 473 e1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5 - l 0.40 0.50 0.60 15.7 19.7 23.6 zd - 0.805 - - 31.7 - y - - 0.076 - - 3 0 o 3 o 6 o 0 o 3 o 6 o 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 9 of 12 AS6C4016 256k x 16 bit super low power cmos sram
48-ball 6mm 8mm tfbga package outline dimension 512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 10 of 12 AS6C4016 256k x 16 bit super low power cmos sram
512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 11 of 12 AS6C4016 256k x 16 bit super low power cmos sram alliance organization vcc range package operating temp speed ns AS6C4016-55zin 256k x 16 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 AS6C4016-55bin 256k x 16 2.7 - 5.5v 48ball tfbga industrial ~ -40 c - 85 c 55 part numbering system as6c 4016 -55 x x n device number package option temperature range 40 = 4m 44pin tsop ii i = industrial low power s ram prefix 1 6 =x16 access t i me 4 8 ball t fbga (-40 to + 85 c) n = lead free ro hs compliant part
512k x 8 bit low power cmos sram january 2007 march 2008 march/2008, v 1.0 alliance memory inc. page 12 of 12 AS6C4016 256k x 16 bit super low power cmos sram copyright ? alliance memory all rights reserved alliance memory, inc 511 taylor way, san carlos, ca 94070, usa phone: 650-610-6800 fax: 650-620-921 1 www.alliancememory.com ? copyright 2008 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks ofalliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to thisdocument and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the datacontained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at anytime, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer . alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability orwarranties related to fitness for a particular purpose, merchantability , or infringement of any intellectual property rights, except as express agreed to inalliance's t erms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance'st erms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user , and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against allclaims arising from such use. ?

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